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Publications



  1. Zhe Wan, S. S. Iyer, "Three-Dimensional Wafer Scale Integration for Ultra Large Scale Cognitive Systems", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 (invited)
  2. Xuefeng Gu, S. S. Iyer, "Unsupervised Learning Using Charge-Trap Transistors", IEEE Electron Device Letters, vol. 38, no. 9, pp. 1204-1207, Sept. 2017. doi: 10.1109/LED.2017.2723319
  3. Adeel A. Bajwa, S. C. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, and S. S. Iyer, "Heterogeneous Integration at Fine Pitch (≤ 10 μm) using Thermal Compression Bonding", Proc. of 67th IEEE Electronic Components and Packaging Technology (ECTC) 2017, Orlando, FL, pp. 1276-1284. doi: 10.1109/ECTC.2017.240
  4. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "“FlexTrate®” – Scaled Heterogeneous Integration on Flexible Biocompatible Substrates", Proc. of 67th IEEE Electronic Components and Technology Conference (ECTC) 2017, Orlando, FL, pp. 649-654. doi: 10.1109/ECTC.2017.226
  5. SivaChandra Jangam, S. Pal, A. Bajwa, S. Parmarti, P. Gupta and S. S. Iyer, "Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme", Proc. of 67th IEEE Electronic Components and Packaging Technology (ECTC) 2017, Orlando, FL, pp. 86-94. doi: 10.1109/ECTC.2017.246
  6. Arvind Kumar, Z. Wan, W. Wilcke, and S. S. Iyer, "Towards Human-Scale Brain Computing Using 3D Wafer Scale Integration," ACM Journal of Emerging Technologies in Computing, vol. 13, no. 3, article no. 45, Apr. 2017.
  7. Adeel A. Bajwa, S. S. Iyer, "Heterogeneous Integration and Scaling for Improved Performance", MEPTEC Report Spring 2017, pp. 18-21, Mar. 2017.
  8. Liheng Zhu, Y. Badr, S. Wang, S. S. Iyer, and P. Gupta, "Assessing Benefits of a Buried Interconnect Layer in Digital Designs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 346-350, Feb. 2017. doi: 10.1109/TCAD.2016.257214
  1. Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
  2. Faraz Khan, E. Cartier, J. C. S. Woo, and S. S. Iyer, "Charge Trap Transistor (CTT); An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies" in IEEE Electron Device Letters, vol. 38, no. 1, Jan. 2017. doi: 10.1109/LED.2016.26334906
  3. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "A New Flexible Device Integration Technology Based on Fan-Out Wafer-Level Packaging", Printed Electronics USA in IDTechEx show, p.96, Nov. 16-17, 2016, Santa Clara, CA, Academic Posters.
  4. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "FlexTrate™: High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics", Proc. NBMC (Nano-Bio Manufacturing Consortium) Workshop: Blood, Sweat and Tears III, Nov. 2-3, 2016, Arlington, VA, invited.
  5. Adeel Bajwa, N. Marathe, S. C. Jangam, S. Pal, P. Y. Liu, M. Goorsky, and S. S. Iyer, "Process development and material characterization of Cu-Cu thermo-compression bonding (TCB) for high-conductivity electrical interconnects," International Symposium on Microelectronics (IMAPS): FALL 2016, vol. 2016, no. 1, pp. 203-208. doi: http://dx.doi.org/10.4071/isom-2016-WA42
  6. Janakiraman Viraraghavan, D. Leu, B. Jayaraman, A. Cestero, R. Kilker, M. Yin, J. Golz, R. R. Tummuru, R. Raghavan, D. Moy, T. Kempanna, F. Khan, T. Kirihata, and S. S. Iyer, "80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity," 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. doi: 10.1109/VLSIC.2016.7573462
  7. Menglu Li, P. Periasamy, K. N. Tu and S. S. Iyer, "Optimized Power Delivery for 3D IC Technology Using Grind Side Redistribution Layers," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 2449-2454. doi: 10.1109/ECTC.2016.217
  8. Prakash Periasamy, Michael Iwatake, Menglu Li, Joyce Liu, Troy Graves-Abe, Thuy Tran Quinn, Subramanian S Iyer, "Electromigration Studies on 6 µm Solid Cu TSV (Via last) in 32 nm SOI Technology," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1364-1369. doi: 10.1109/ECTC.2016.293
  9. Brittany Hedrick, V. Sukumaran, B. Fasano, C. Tessler, J. Garant, J. Lubguban, S. Knickerbocker, M. Cranmer, K. Ramachandran, I. Melville, D. Berger, M. Angyal, R. Indyk, D. Lewison, C. Arvin, L. Guerin, M. Cournoyer, M. P. L. Ouellet, J. Audet, F. Baez, S. Li, and S. S. Iyer, "End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 283-288. doi: 10.1109/ECTC.2016.261
  10. John Safran, G. N. K. Rangan, V. N. R. Vanukuru, S. Torgal, V. Chaturvedi, S. Butt, G. Maier, A. Cestero, T. Tran-Quinn, J. Nag, S. Rosenblatt, N. Robson, M. Angyal, T. Graves-Abe, D. Berger, J. Pape, and S. S. Iyer, "3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1451-1456. doi: 10.1109/ECTC.2016.324
  11. Toshiaki Kirihata, J. Golz, M. Wordeman, P. Batra, G. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Iyer, "Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 373-384, Sept. 2016. doi: 10.1109/JETCAS.2016.2547738
  12. Subramanian S. Iyer, "Heterogeneous Integration for Performance and Scaling," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no.7, pp. 973-982, Jul. 2016. doi: 10.1109/TCPMT.2015.2511626
  1. Faraz Khan, E. Cartier, C. Kothandaraman, J. C. Scott, J. C. S. Woo, and S. S. Iyer, "The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs," in Electron Device Letters, IEEE , vol. 37, no. 1, pp. 88-91, Jan. 2016. doi: 10.1109/LED.2015.2504952
  2. Subramanian S. Iyer, T. Kirihata, "Three-Dimensional Integration: A Tutorial for Designers," in Solid-State Circuits Magazine, IEEE , vol. 7, no. 4, pp. 63-74, Fall 2015. doi: 10.1109/MSSC.2015.2474235
  3. Subramanian S. Iyer, "Monolithic three-dimensional integration for memory scaling and neuromorphic computing," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, 2015, pp. 1-7. doi: 10.1109/S3S.2015.7333508
  4. Subramanian S. Iyer, "Invited talk: Some challenges in scaling 3D ICs to a broader application set," 2015 International 3D Systems Integration Conference (3DIC), Sendai, Japan, 2015, pp. TS1.1.1-TS1.1.1. doi: 10.1109/3DIC.2015.7334470
  5. Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
  6. Katsuyuki Sakuma, K. Tunga, B. Webb, K. Ramachandran, M. Interrante, H. Liu, M. Angyal, D. Berger, J. Knickerbocker, and S. S. Iyer, "An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates," 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp. 318-324. doi: 10.1109/ECTC.2015.7159611
  7. Chandrasekara Kothandaraman, X. Chen, D. Moy, D. Lea, S. Rosenblatt, F. Khan, D. Leu, T. Kirihata, D. Ioannou, G. La Rosa, J. Johnson, N. Robson, and S. S. Iyer, "Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. MY.2.1-MY.2.4. doi: 10.1109/IRPS.2015.7112816
  8. Muqta G. Farooq, G. La. Rosa, F. Chen, P. Periasamy, T. Graves-Abe, C. Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, J. Safran, S. Ghosh, S. Mittl, D. Ioannou, C. Graas, D. Berger, and S. S. Iyer, "Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. 4C.1.1-4C.1.8. doi: 10.1109/IRPS.2015.7112732
  9. Subramanian S. Iyer, "Three-dimensional integration: An industry perspective," Materials challenges in 3D IC technology, MRS Bulletin, vol. 40, no. 3, pp. 225-232, Mar. 2015.