Login
Signup

Publications



  1. Rachel M. Brewer, J. Cox, D. R. Ball, S. Moran, B. D. Sierawski, P. F. Wang, E. X. Zhang, D. M. Fleetwood, R. D. Schrimpf, S. S. Iyer, and M. L. Alles, "Total Ionizing Dose Response of 22nm FDSOI Charge-Trap Transistors", 2020 IEEE Nuclear and Space Radiation Effects Conference, Dec. 1-4, 2020, Santa Fe, NM. (Accepted)
  2. N.Shakoorzadeh, S.S.Iyer, “Atomic Layer Deposited Al­2O3 for Encapsulation of the Silicon Interconnect Fabric “, 2020 Semiconductor Research Corporation Technical Conference (SRC TechCon) TechCon
  3. S. Jangam and S. S. Iyer, "A Signaling Figure of Merit (s-FoM) for Advanced Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2020.3022760
  4. K. T. Kannan and S. S. Iyer, "Deep Trench Capacitors in Silicon Interconnect Fabric," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 2295-2301, doi: 10.1109/ECTC32862.2020.00358.
  5. A. Dasgupta, A. Alam, G. Ouyang, S. Jangam and S. S. Iyer, "Antenna on Silicon Interconnect Fabric," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 1788-1794, doi: 10.1109/ECTC32862.2020.00279.
  6. S. Benedict, A. Nagarajan, T. Kumar, A. Alam, M. S. Illango, G. Ezhilarasu, C. S. Prajapati, N. Bhat, and S. S. Iyer, "Heterogenous Integration of MEMS Gas Sensor using FOWLP : Personal Environment Monitors," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 824-828, doi: 10.1109/ECTC32862.2020.00134.
  7. S. Jangam, U. Rathore, S. Nagi, D. Markovic and S. S. Iyer, "Demonstration of a Low Latency (<20 ps) Fine-pitch (≤10 μm) Assembly on the Silicon Interconnect Fabric," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 1801-1805, doi: 10.1109/ECTC32862.2020.00281.
  8. Y. Yang, C. Hu, J. Green, P. Zhang, N. Shakoorzadeh, P. Ambhore, U. Mogera, N. Ni, K. L. Wang, and S. S. Iyer, "Demonstration of Superconducting Interconnects on the Silicon Interconnect Fabric Using Thermocompression Bonding," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 1861-1866, doi: 10.1109/ECTC32862.2020.00291.
  9. G. Ezhilarasu, A. Paranjpe, J. Lee, F. Wei and S. S. Iyer, "A Heterogeneously Integrated, High Resolution and Flexible Inorganic μLED Display using Fan-Out Wafer-Level Packaging," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 677-684, doi: 10.1109/ECTC32862.2020.00112.
  10. N. Shakoorzadeh, K. Sahoo, Y.T. Yang, and S.S. Iyer, "Atomic Layer Deposited Al2O3 Encapsulation for the Silicon Interconnect Fabric." 2020 IEEE 70th Electronic Components and Technology Conference (ECTC) (2020): 1241-1246, doi: 10.1109/ectc32862.2020.00198.
  11. A. Alam, M. Molter, B. Gaonkar, A. Hanna, R. Irwin, S. Benedict, G. Ezhilarasu, L. Macyszyn, M. S. Joseph, and S. S. Iyer, "A High Spatial Resolution Surface Electromyography (sEMG) System Using Fan-Out Wafer-Level Packaging on FlexTrate™," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 985-990, doi: 10.1109/ECTC32862.2020.00160.
  12. R. Irwin, Y. Hu, A. Alam, S. Benedict, T. Fisher and S. S. Iyer, "Nanowire Impregnated Poly-dimethyl Siloxane for Flexible, Thermally Conductive Fan-Out Wafer-Level Packaging," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 1548-1553, doi: 10.1109/ECTC32862.2020.00243.
  13. S. Roymohapatra, G. Gore, A. Yadav, M. Patil, K. Rengarajan, S. S. Iyer, M. Baghini, "A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 5, pp. 1073-1083, May 2020, doi: 10.1109/TCAD.2019.2907879.
  14. Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, and Puneet Gupta, "Design Space Exploration for Chiplet-Assembly-Based Processors," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 4, pp. 1062-1073, April 2020.
  15. Steven Moran, J. Cox, Z. Wan, R. Brewer, E. X. Zhang, B. Sierawski, J. Woo, and S. S. Iyer, "Impacts of Perturbation on a Charge Trap Transistor Analog Neural Network", GOMACTech-20, Microelectronics for a New Decade: Global Competition and Near-Peer Challenges, March 16-19, 2020, San Diego, CA. (Accepted)
  16. Arsalan Alam, Michael Molter, and Subramanian S. Iyer, "Development of FlexTrateTM using Fan-Out-Wafer-Level-Packaging (FOWLP) and to demonstrate fully integrated multi-channel flexible surface Electromyography (sEMG) system," Flex 2020, San Jose, CA, February 24-27, 2020
  17. Faraz Khan, "Charge Trap Transistors (CTT): A Process/Mask-Free Secure Embedded Non-Volatile Memory for 14 nm FinFET Technologies and Beyond", Microelectronics Reliability and Qualification Workshop (MRQW), 2020 [Invited].
  1. Rachel Brewer, S. Moran, J. Cox, B. Sierawski, M. McCurdy, E. X. Zhang, S. S. Iyer, R. D. Schrimpf, M. Alles, and R. Reed, "The impact of proton-induced single events on image classification in a neuromorphic architecture," in IEEE Transactions on Nuclear Science, vol. 67, no. 1, pp. 108-115, Dec. 2019.
  2. S. S. Iyer, S. Jangam, and B. Vaisband, "Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems," in IBM Journal of Research and Development, vol. 63, no. 6, pp. 5:1-5:16, 1 Nov.-Dec. 2019.
  3. Boris Vaisband and S. S. Iyer, "Global and Semi-Global Communication on Silicon Interconnect Fabric", Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip, pp. 15:1-15:5, October 2019.
  4. Xuefeng Gu, Z. Wan and S. S. Iyer, "Charge-Trap Transistors for CMOS-Only Analog Memory," in IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4183-4187, Oct. 2019.
  5. P. Gupta and S. S. Iyer, "Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric," in IEEE Spectrum, vol. 56, no. 10, pp. 28-33, Oct. 2019, doi: 10.1109/MSPEC.2019.8847587.
  6. Rachel Brewer, S. Moran, J. Cox, B. Sierawski, M. McCurdy, S. S. Iyer, M. Alles, and R. Reed, "The impact of proton-induced single events on image classification in a neuromorphic architecture," 2019 IEEE Nuclear and Space Radiation Effects Conference, July 8-12, 2019, San Antonio, TX.
  7. Faraz Khan, M. Han, D. Moy, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata, J. C. S. Woo, and S. S. Iyer, "Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies," IEEE Electron Device Letters, July 2019.
  8. Faraz Khan, D. Moy, D. Anand, E. Hunt-Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, and T. Kirihata, "Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond," IEEE Symposium on VLSI Technology, Kyoto, Japan, June 2019.
  9. Boris Vaisband and S. S. Iyer, "Communication Considerations for Silicon Interconnect Fabric," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, June 2019.
  10. Siva Chandra Jangam, A. Bajwa, U. Mogera, P. Ambhore, T. Colosimo, T. Palumbo, D. DeAngelis, B. Chylak and S. S. Iyer, "Fine-Pitch (≤10 µm) Direct Cu-Cu Interconnects using In-situ Formic Acid Vapor Treatment", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  11. Pranav Ambhore, B. Vaisband, U. Mogera, U. Shah, T. Fisher, M. Goorsky, and S. S. Iyer, "PowerTherm Attachment Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  12. Meng-Hsiang Liu, B. Vaisband, A. Hanna, Y. Luo, Z. Wan and S. S. Iyer, "Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  13. Niloofar Shakoorzadeh, S. Jangam, P. Ambhore, H. Chien, A. Hanna, S. S. Iyer, "Reliability Studies of Si Interconnect Fabric (Si-IF)", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  14. Eric Sorensen, B. Vaisband, S. Jangam, T. Shirley, and S. S. Iyer, "Integration and Characterization of InP Dies on Silicon Interconnect Fabric", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  15. Arsalan Alam, A. Hanna, R. Irwin, G. Ezhilarasu, H. Boo, Y. Hu, C. W. Wong, T. S. Fisher, and S. S. Iyer, "Heterogeneously Integrated Foldable Display on Elastomeric Substrate Based on Fan-Out Wafer Level Packaging", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  16. Kannan K. Thankappan, B. Vaisband, S. S. Iyer, "On-Chip ESD Monitor", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  17. Goutham Ezhilarasu, A. Hanna, A. Paranjpe, and S. Iyer, "High Yield Precision Transfer and Assembly of GaN µLEDs using Laser Assisted Micro Transfer Printing", IEEE 69th Electronic Components and Technology Conference (ECTC), May 28-31, 2019, Las Vegas, NV.
  18. Ujash Shah, U. Mogera, P. Ambore, B. Vaisband, S. S. Iyer, and T. S. Fisher, "Dynamic Thermal Management for Silicon Interconnect Fabric using Flash Cooling," Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May 2019.
  19. N. Shakoorzadeh, A. Hanna, S. S. Iyer, "Bilayer Passivation Film For Cu Interconnects on Si Interconnect Fabric", IEEE International Reliability Physics Symposium, March 31 - April 4, 2019, Monterey, CA.
  20. Kannan K. Thankappan, A. Bajwa, B. Vaisband, S. Jangam, and S. S. Iyer, "Reliability Evaluation of Silicon Interconnect Fabric Technology", IEEE International Reliability Physics Symposium, March 31 - April 4, 2019, Monterey, CA.
  21. Faraz Khan, E. Hunt-Schroeder, D. Moy, D. Anand, R. Katz, D. Leu, J. Fifield, N. Robson, S. Ventrone, T. Kirihata, "A Multi-Time Programmable Embedded Memory Technology in a Native 14nm FINFET Process using Charge Trap Transistors (CTTs)," Proceedings of the Government Microcircuit Applications & Critical Technology (GOMACTech) Conference, March 2019.
  22. Steven Moran, J. Cox, R. Brewer, B. Sierawski, and S. S. Iyer, "Radiation Effects on Brain-Inspired Computing," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM.
  23. Zhe Wan, S. Moran, X. Gu, J. Cox, and S. S. Iyer, "Characterization Approaches to Test the Robustness of Neuromorphic Systems," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM.
  24. Subramanian S. Iyer, S. Jangam, and B. Vaisband, "From Homogeneous SoCs to Heterogeneous SoWs," Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2019.
  25. Bilwaj Gaonkar, J. Beckett, D. Villaroman, C. Ahn, M. Edwards, S. Moran, M. Attiah, D.Babayan, C. Ames, J. P. Villablanca, N. Salamon, A. Bui, and L. Macyszyn, "Quantitative analysis of neural foramina in the lumbar spine: an imaging informatics and machine learning study," in Radiology: Artificial Intelligence, vol. 1, no. 2, Mar. 2019.
  26. Arsalan Alam and S. S. Iyer, "Heterogeneously Integrated Foldable Display on Elastomeric Substrate Based on Fan-Out Wafer Level Packaging", Flex 2019, February 18-21, 2019, Monterey, CA.
  27. Saptadeep Pal, D. Petrisko, M. Tomei, P. Gupta, S. S. Iyer, and R. Kumar, "Architecting Waferscale Processors: A GPU Case Study", in 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 16-20, 2019, Washington D.C., USA.
  1. Goutham Ezhilarasu, A. Hanna, R. Irwin, A. Alam, and S. S. Iyer, "A Flexible, Heterogeneously Integrated Wireless Powered System for Bio-Implantable Applications using Fan-Out Wafer-Level Packaging," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 29.7.1-29.7.4. doi: 10.1109/IEDM.2018.8614705
  2. Pranav Ambhore, K. Mani, B. Beekley, N. Malik, K. Schjølberg-Henriksen, S. Iyer, and M. S. Goorsky, "The Synergistic Roles of Temperature and Pressure in Thermo-Compression Bonding of Au," ECS Trans. 2018 volume 86, Issue 5, 129-135.
  3. Zhe Wan, K. Winstel, A Kumar and S. S. Iyer, "Low-Temperature Wafer Bonding for Three- Dimensional Wafer-Scale Integration," 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Burlingame, CA, 2018.
  4. Takafumi Fukushima, A. Alam, A. Hanna, S. Jangam, A. Bajwa, and S. S. Iyer, "Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 10, pp. 1738-1746, Oct. 2018.
  5. Zhe Wan and S. Iyer, "Fine-Pitch Integration Technology for Cognitive System Scaling," 2018 Semiconductor Research Corporation Technical Conference (SRC TechCon) TechCon, Austin, TX, 2018.
  6. Bau Pham, B. Gaonkar, W. Whitehead, S. Moran, Q. Dai, L. Macyszyn, and V. R. Edgerton, "Cell Counting and Segmentation of Immunohistochemical Images in the Spinal Cord: Comparing Deep Learning and Traditional Approaches," 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Jul. 2018.
  7. Adeel Bajwa, S. Jangam, S. Pal, B. Vaisband, R. Irwin, M. Goorsky, and S. S. Iyer "Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) assembly," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
  8. Takafumi Fukushima, Y. Susumago, H. Kino, T. Tanaka, A. Alam, A. Hanna, and S. S. Iyer "Self-Assembly Technologies for FlexTrate™," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
  9. Amir Hanna, T. Fukushima, A. Alam, S. Moran, W. Whitehead, S. Jangam, R. Irwin, A. Bajwa, S. Pal, and S. S. Iyer, "Extremely Flexible (1mm bending radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-based Interconnects," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
  10. SivaChandra Jangam, A. Bajwa, K. K. Thankappan, P. Kittur, and S. S. Iyer, "Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
  11. Rachel M. Brewer, S. Moran, J. Cox, M. McCurdy, R. Erbrick, M. Alles, R. Reed, S. S. Iyer, and B. Sierawski, "Proton-Induced Classification Changes in a Neuromorphic Computing System," 2018 Single Event Effects (SEE) Symposium, May 20-24, 2018, San Diego, CA.
  12. Subramanian S. Iyer and Adeel Ahmad Bajwa, "Reliability challenges in advance packaging," 2018 IEEE International Reliability Physics Symposium (IRPS), March 11-15, 2018.
  13. William Whitehead, S. Moran, B. Gaonkar, L. Macyszyn, and S. S. Iyer, "A Deep Learning Approach to Spine Segmentation using a Feed-forward Chain of Pixel-wise Convolutional Networks," IEEE International Symposium on Biomedical Imaging (ISBI), April 4-7, 2018, Washington D.C.
  14. B. Vaisband, A. Bajwa, and S. S. Iyer, “Network on Interconnect Fabric,” Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2018.
  15. Steven Moran, B. Gaonkar, W. Whitehead, A. Wolk, L. Macyszyn, and S. S. Iyer, "Deep Learning for Medical Image Segmentation – Using the IBM TrueNorth Neurosynaptic System", SPIE Medical Imaging, Feb 10-15, 2018.
  16. Saptadeep Pal, D. Petrisko, A. Bajwa, P. Gupta, S. S. Iyer, and R. Kumar "A Case for Packageless Processors", 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 24-28, 2018, Vienna, Austria.
  17. Amir Hanna, "Flexible (1mm bending radius) Biocompatible Heteregeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6µm) and Reliable Flexible Cu-based Interconnects", Semi 2018 Flex, February 12-15, 2018, Monterey, CA.
  18. Elaheh Rabiei, M. White, A. Mosleh, S. Lyer and J. Woo, "Component Reliability Modeling Through the Use of Bayesian Networks and Applied Physics-based Models," 2018 Annual Reliability and Maintainability Symposium (RAMS), Reno, NV, 2018, pp. 1-7.
  1. Faraz Khan, E. Cartier, J. C. S. Woo, and S. S. Iyer, "Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies," IEEE Electron Device Letters, vol. 38, no. 1, 2017. doi: 10.1109/LED.2016.26334906
  2. Saptadeep Pal, S. S. Iyer, and P. Gupta, "Advanced packaging and heterogeneous integration to reboot computing," in IEEE International Conference on Rebooting Computing (ICRC), November 8-9, 2017, Washington, DC, USA. (Invited)
  3. Zhe Wan and S. S. Iyer, "Three-dimensional wafer scale integration for ultra-large-scale cognitive systems," 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, 2017, pp. 1-2.
  4. R. M. Walker, L. Rieth, S. S. Iyer, A. A. Bajwa, J. Silver, T. Ahmed, N. Tasneem, M. Sharma, A. Gardner, "Integrated neural interfaces," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017, pp. 1045-1048. doi: 10.1109/MWSCAS.2017.8053106
  5. Xuefeng Gu, S. S. Iyer, "Unsupervised Learning Using Charge-Trap Transistors", IEEE Electron Device Letters, vol. 38, no. 9, pp. 1204-1207, Sept. 2017. doi: 10.1109/LED.2017.2723319
  6. Arsalan Alam, T. Fukushima, A. Hanna, S. C. Jangam, A. Bajwa, and S. S. Iyer, "FlexTrate™: For next generation high performance flexible systems", FlexTech Flexible & Printed Electronics Conference & Exhibition (2017 Flex), June 19-22, 2017, Monterey, CA.
  7. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "“FlexTrate®” – Scaled Heterogeneous Integration on Flexible Biocompatible Substrates", Proc. of 67th IEEE Electronic Components and Technology Conference (ECTC) 2017, Orlando, FL, pp. 649-654. doi: 10.1109/ECTC.2017.226
  8. Adeel A. Bajwa, S. C. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, and S. S. Iyer, "Heterogeneous Integration at Fine Pitch (≤ 10 μm) using Thermal Compression Bonding", Proc. of 67th IEEE Electronic Components and Packaging Technology (ECTC) 2017, Orlando, FL, pp. 1276-1284. doi: 10.1109/ECTC.2017.240
  9. SivaChandra Jangam, S. Pal, A. Bajwa, S. Parmarti, P. Gupta and S. S. Iyer, "Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme", Proc. of 67th IEEE Electronic Components and Packaging Technology (ECTC) 2017, Orlando, FL, pp. 86-94. doi: 10.1109/ECTC.2017.246
  10. Arvind Kumar, Z. Wan, W. Wilcke, and S. S. Iyer, "Towards Human-Scale Brain Computing Using 3D Wafer Scale Integration," ACM Journal of Emerging Technologies in Computing, vol. 13, no. 3, article no. 45, Apr. 2017.
  11. Adeel A. Bajwa, S. S. Iyer, "Heterogeneous Integration and Scaling for Improved Performance", MEPTEC Report Spring 2017, pp. 18-21, Mar. 2017.
  12. Liheng Zhu, Y. Badr, S. Wang, S. S. Iyer, and P. Gupta, "Assessing Benefits of a Buried Interconnect Layer in Digital Designs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 2, pp. 346-350, Feb. 2017. doi: 10.1109/TCAD.2016.257214
  1. Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
  2. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "A New Flexible Device Integration Technology Based on Fan-Out Wafer-Level Packaging", Printed Electronics USA in IDTechEx show, p.96, Nov. 16-17, 2016, Santa Clara, CA, Academic Posters.
  3. Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "FlexTrate™: High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics", Proc. NBMC (Nano-Bio Manufacturing Consortium) Workshop: Blood, Sweat and Tears III, Nov. 2-3, 2016, Arlington, VA, invited.
  4. Adeel Bajwa, N. Marathe, S. C. Jangam, S. Pal, P. Y. Liu, M. Goorsky, and S. S. Iyer, "Process development and material characterization of Cu-Cu thermo-compression bonding (TCB) for high-conductivity electrical interconnects," International Symposium on Microelectronics (IMAPS): FALL 2016, vol. 2016, no. 1, pp. 203-208. doi: http://dx.doi.org/10.4071/isom-2016-WA42
  5. Janakiraman Viraraghavan, D. Leu, B. Jayaraman, A. Cestero, R. Kilker, M. Yin, J. Golz, R. R. Tummuru, R. Raghavan, D. Moy, T. Kempanna, F. Khan, T. Kirihata, and S. S. Iyer, "80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity," IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, 2016, pp. 1-2. doi: 10.1109/VLSIC.2016.7573462
  6. Menglu Li, P. Periasamy, K. N. Tu and S. S. Iyer, "Optimized Power Delivery for 3D IC Technology Using Grind Side Redistribution Layers," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 2449-2454. doi: 10.1109/ECTC.2016.217
  7. Brittany Hedrick, V. Sukumaran, B. Fasano, C. Tessler, J. Garant, J. Lubguban, S. Knickerbocker, M. Cranmer, K. Ramachandran, I. Melville, D. Berger, M. Angyal, R. Indyk, D. Lewison, C. Arvin, L. Guerin, M. Cournoyer, M. P. L. Ouellet, J. Audet, F. Baez, S. Li, and S. S. Iyer, "End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 283-288. doi: 10.1109/ECTC.2016.261
  8. Prakash Periasamy, Michael Iwatake, Menglu Li, Joyce Liu, Troy Graves-Abe, Thuy Tran Quinn, Subramanian S Iyer, "Electromigration Studies on 6 µm Solid Cu TSV (Via last) in 32 nm SOI Technology," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1364-1369. doi: 10.1109/ECTC.2016.293
  9. John Safran, G. N. K. Rangan, V. N. R. Vanukuru, S. Torgal, V. Chaturvedi, S. Butt, G. Maier, A. Cestero, T. Tran-Quinn, J. Nag, S. Rosenblatt, N. Robson, M. Angyal, T. Graves-Abe, D. Berger, J. Pape, and S. S. Iyer, "3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1451-1456. doi: 10.1109/ECTC.2016.324
  10. Toshiaki Kirihata, J. Golz, M. Wordeman, P. Batra, G. W. Maier, N. Robson, T. L. Graves-abe, D. Berger, and S. S. Iyer, "Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 373-384, Sept. 2016. doi: 10.1109/JETCAS.2016.2547738
  11. Arvind Kumar, Z. Wan, W. Wilcke, and S. S. Iyer. "3D Wafer Scale Integration: A Scaling Path to an Intelligent Machine." Neuro-Inspired Computational Elements, Berkeley, CA (2016).
  12. Subramanian S. Iyer, "Heterogeneous Integration for Performance and Scaling," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no.7, pp. 973-982, Jul. 2016. doi: 10.1109/TCPMT.2015.2511626
  13. Faraz Khan, E. Cartier, C. Kothandaraman, J. C. Scott, J. C. S. Woo, and S. S. Iyer, "The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs," Electron Device Letters, IEEE , vol. 37, no. 1, pp. 88-91, Jan. 2016. doi: 10.1109/LED.2015.2504952
  14. G. Fredeman et al., "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016.
  1. Faraz Khan, E. Cartier, C. Kothandaraman, J. C. Scott, J. C. S. Woo, and S. S. Iyer, "The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs," Electron Device Letters, IEEE , vol. 37, no. 1, pp. 88-91, Jan. 2016. doi: 10.1109/LED.2015.2504952
  2. Subramanian S. Iyer, T. Kirihata, "Three-Dimensional Integration: A Tutorial for Designers," in Solid-State Circuits Magazine, IEEE , vol. 7, no. 4, pp. 63-74, Fall 2015. doi: 10.1109/MSSC.2015.2474235
  3. Subramanian S. Iyer, "Monolithic three-dimensional integration for memory scaling and neuromorphic computing," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, 2015, pp. 1-7. doi: 10.1109/S3S.2015.7333508
  4. Subramanian S. Iyer, "Invited talk: Some challenges in scaling 3D ICs to a broader application set," 2015 International 3D Systems Integration Conference (3DIC), Sendai, Japan, 2015, pp. TS1.1.1-TS1.1.1. doi: 10.1109/3DIC.2015.7334470
  5. Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
  6. Katsuyuki Sakuma, K. Tunga, B. Webb, K. Ramachandran, M. Interrante, H. Liu, M. Angyal, D. Berger, J. Knickerbocker, and S. S. Iyer, "An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates," 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp. 318-324. doi: 10.1109/ECTC.2015.7159611
  7. Chandrasekara Kothandaraman, X. Chen, D. Moy, D. Lea, S. Rosenblatt, F. Khan, D. Leu, T. Kirihata, D. Ioannou, G. La Rosa, J. Johnson, N. Robson, and S. S. Iyer, "Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. MY.2.1-MY.2.4. doi: 10.1109/IRPS.2015.7112816
  8. Muqta G. Farooq, G. La. Rosa, F. Chen, P. Periasamy, T. Graves-Abe, C. Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, J. Safran, S. Ghosh, S. Mittl, D. Ioannou, C. Graas, D. Berger, and S. S. Iyer, "Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. 4C.1.1-4C.1.8. doi: 10.1109/IRPS.2015.7112732
  9. Subramanian S. Iyer, "Three-dimensional integration: An industry perspective," Materials challenges in 3D IC technology, MRS Bulletin, vol. 40, no. 3, pp. 225-232, Mar. 2015.