Faraz Khan, "A Multi-Time Programmable Embedded Memory Technology in a Native 14nm FINFET Process using Charge Trap Transistors (CTTs)," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 2019, Albuquerque, NM. (Accepted)
Steven Moran, J. Cox, R. Brewer, B. Sierawski, and S. S. Iyer, "Radiation Effects on Brain-Inspired Computing," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM (Accepted).
Zhe Wan, S. Moran, X. Gu, J. Cox, and S. S. Iyer, "Characterization Approaches to Test the Robustness of Neuromorphic Systems," GOMACTech-19, Artificial Intelligence & Cyber Security: Challenges and Opportunities for the Government, March 25-28, 2019, Albuquerque, NM (Accepted).
Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, and Rakesh Kumar, "Architecting Waferscale Processors: A GPU Case Study", in 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 16-20, 2019, Washington D.C., USA (Accepted)
Zhe Wan, K. Winstel, A Kumar and S. S. Iyer, "Low-Temperature Wafer Bonding for Three- Dimensional Wafer-Scale Integration," 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Burlingame, CA, 2018.
Bau Pham, B. Gaonkar, W. Whitehead, S. Moran, Q. Dai, L. Macyszyn, and V. R. Edgerton, "Cell Counting and Segmentation of Immunohistochemical Images in the Spinal Cord: Comparing Deep Learning and Traditional Approaches," 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Jul. 2018.
Takafumi Fukushima, Yuki Susumago, Hisashi Kino, Tetsu Tanaka, Arsalan Alam, Amir Hanna, and Subramanian S. Iyer "Self-Assembly Technologies for FlexTrate™," IEEE 68th IEEE Electronic Components and Technology Conference (ECTC), May 29-June 1, 2018, San Diego, CA.
Rachel M. Brewer, S. Moran, J. Cox, M. McCurdy, R. Erbrick, M. Alles, R. Reed, S. S. Iyer, and B. Sierawski, "Proton-Induced Classification Changes in a Neuromorphic Computing System," 2018 Single Event Effects (SEE) Symposium, May 20-24, 2018, San Diego, CA.
Saptadeep Pal, D. Petrisko, A. Bajwa, P. Gupta, S. S. Iyer, and R. Kumar "A Case for Packageless Processors", 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 24-28, 2018, Vienna, Austria.
R. M. Walker, L. Rieth, S. S. Iyer, A. A. Bajwa, J. Silver, T. Ahmed, N. Tasneem, M. Sharma, A. Gardner, "Integrated neural interfaces," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017, pp. 1045-1048. doi: 10.1109/MWSCAS.2017.8053106
Arsalan Alam, T. Fukushima, A. Hanna, S. C. Jangam, A. Bajwa, and S. S. Iyer, "FlexTrate™: For next generation high performance flexible systems", FlexTech Flexible & Printed Electronics Conference & Exhibition (2017 Flex), June 19-22, 2017, Monterey, CA.
Chandrasekara Kothandaraman, S. Rosenblatt, J. Safran, P. Oldiges, P. Kulkarni-Kerber, J. Xumalo, W. Landers, J. Liu, J. A. Oakley, S. Butt, T. L. Graves-Abe, N. Robson, M. G. Farooq, D. Berger and S. S. Iyer, "Vertical channel devices enabled by through silicon via (TSV) technologies," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 9.6.1-9.6.4. doi: 10.1109/IEDM.2016.7838384
Takafumi Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, and S. S. Iyer, "A New Flexible Device Integration Technology Based on Fan-Out Wafer-Level Packaging", Printed Electronics USA in IDTechEx show, p.96, Nov. 16-17, 2016, Santa Clara, CA, Academic Posters.
Brittany Hedrick, V. Sukumaran, B. Fasano, C. Tessler, J. Garant, J. Lubguban, S. Knickerbocker, M. Cranmer, K. Ramachandran, I. Melville, D. Berger, M. Angyal, R. Indyk, D. Lewison, C. Arvin, L. Guerin, M. Cournoyer, M. P. L. Ouellet, J. Audet, F. Baez, S. Li, and S. S. Iyer, "End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 283-288. doi: 10.1109/ECTC.2016.261
Gregory Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee, D. Rainey, M. Sperling, M. Whalen, S. Burns, R. Tummuru, H. Ho, A. Cestero, N. Arnold, B. Khan, T. Kirihata, and S. S. Iyer, "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873
Muqta G. Farooq, G. La. Rosa, F. Chen, P. Periasamy, T. Graves-Abe, C. Kothandaraman, C. Collins, W. Landers, J. Oakley, J. Liu, J. Safran, S. Ghosh, S. Mittl, D. Ioannou, C. Graas, D. Berger, and S. S. Iyer, "Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability," 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. 4C.1.1-4C.1.8. doi: 10.1109/IRPS.2015.7112732