Interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes, that will shrink system footprint and improve power and performance.
University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in...
The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.