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Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrate TM ) was used to assemble 625 dies with co-planarity and tilt <1µm, average die-shift of 3.28 µm with σ < 2.23 µm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in...

Characterization of Fine Pitch Interconnections (<=10um) on Silicon Interconnect Fabric for Heterogeneous Integration - Siva Jangam

The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets. We propose a fine-pitch integration scheme where dielets are attached to the Si-IF with fine-pitch interconnects (≤10 µm) at short inter-dielets spacings (≤100 µm) using direct metal-metal Thermal Compression Bonding process (TCB). As a result, short links on Si-IF (≤ 500 µm) are used for inter-dielet communication, reducing the latency to ≤ 35 ps. We experimentally demonstrated the measured insertion loss in these short Si-IF links (≤ 500 µm) is ≤2 dB for frequencies up to 30 GHz. As a result, we show that assemblies on...

Dynamically Controlled Flow Loop to Benchmark Rapid Transient Cooling Utilizing Flash Boiling for High Heat Flux Electronic Systems - Ujash Shah

Transient cooling of high-heat-flux components presents significant challenges. Flash cooling is a promising approach to mitigate temperature spikes due to episodic heat pulses in electronic components. We present a flow loop concept that provides a flexible and reliable setup to quantify and benchmark flash cooling. The testbed is dynamically controlled through LabVIEW workbench using a micro-controller to manage the transient response of the system. The quick response of the loop is achieved with the help of flow control components with a response time of a few milliseconds. The setup is compatible with fluids for...

IEEE 68th Electronic Components and Technology Conference Best Student Paper Award

Siva Chandra Jangam (Advisor: Prof. Subramanian Iyer, UCLA Center for Integration and Performance Scaling (CHIPS)) won the ECTC Best Student Paper Award for the paper titled “Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme” at the 2018 IEEE 68th Electronic Components and Technology Conference held in San Diego, CA. This latest work describes the performance and power benefits of the Fine Pitch integration scheme on a Silicon Interconnect Fabric (Si IF) proposed by a Simple Universal Parallel intERface (SuperCHIPS) protocol enabled by fine pitch dielet to interconnect fabric assembly. Dramatic improvements in bandwidth, latency, and power are achievable...

Prof. Subramanian S. Iyer and Prof. Alan N. Willson, Jr. have awarded to the rank of NAI Fellows.

The 2017 National Academy of Inventors (NAI) Fellows Selection Committee and Board of Directors have awarded Dr. Subramanian S. Iyer and Dr. Alan N. Willson, Jr., of the Electrical & Computer Engineering Department, to the rank of NAI Fellows, the nominations of which were submitted by Dr. Asad M. Madni. Both have been chosen as they have “demonstrated a highly prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.” The Fellows Induction Ceremony will be held on April 5, 2018 at...

Packageless processors; improving AI accuracy; superconductivity rules. BY: ANN STEFFORA MUTSCHLER

Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. However, a team of researchers from the Department of Electrical and Computer Engineering from the University of California, Los Angeles along with colleagues from the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by...

4 Strange New Ways to Compute

Prof. Gupta's invited talk on packageless computing systems at International Conference on Rebooting Computing gets covered on IEEE Spectrum website.

Universities Obtain New Funding from Nano-Bio Manufacturing Consortium

University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in portable devices such as smart phones. It offers the advantages of true heterogeneous integration of different dies, including high performance electronics, tight pitch interconnects, and components (such as low profile passives) with a short turn-around, scalable, manufacturing process.

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?

Making 2.5D, Fan-Outs Cheaper

Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.

IFTLE 301 Are Silicon Circuit Boards in our Future?

The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance.

ECTC 2016: Is the Life after Moore’s Law?

Is Moore’s Law dead or not? It depends on your perspective. Last week at ECTC 2016, Rozalia Beica, Dow Electronic Materials, gathered a prestigious group of senior executives from the world’s leading microelectronics research institutes to discuss Life after Moore’s Law. Panelists included Marie-Noelle Semeria, CEA-Leti; Dim Lee Kwong, IME; Luc van den hove, imec; CP Wong, NCAP; and Subu Iyer, UCLA CHIPS. Each discussed the strategy they will pursue to continue innovations for next-generation computing technologies, with or without Moore’s Law.

Semiconductor Engineering “Why Use A Package” by Ed Sperling

UCLA’s Subramaniam Iyer believes the industry needs to rethink its future direction.

3DInCites “System-level Scaling: UCLA’s Answer to Extending Moore’s Law” by Francoise von Trapp

“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about scaling the system.” ~ Excerpt from the letter to attendees of the CHIPS kick-off meeting at UCLA. This is the mission of the new Center for Heterogeneous Integration and Performance Scaling (CHIPS) that was launched with a kick-off meeting at UCLA on November 2, 2015.