The 2017 National Academy of Inventors (NAI) Fellows Selection Committee and Board of Directors have awarded Dr. Subramanian S. Iyer and Dr. Alan N. Willson, Jr., of the Electrical & Computer Engineering Department, to the rank of NAI Fellows, the nominations of which were submitted by Dr. Asad M. Madni. Both have been chosen as they have “demonstrated a highly prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.” The Fellows Induction Ceremony will be held on April 5, 2018 at...
Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. However, a team of researchers from the Department of Electrical and Computer Engineering from the University of California, Los Angeles along with colleagues from the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by...
Prof. Gupta's invited talk on packageless computing systems at International Conference on Rebooting Computing gets covered on IEEE Spectrum website.
University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in portable devices such as smart phones. It offers the advantages of true heterogeneous integration of different dies, including high performance electronics, tight pitch interconnects, and components (such as low profile passives) with a short turn-around, scalable, manufacturing process.
The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.
The CHIPS mission is to interpret and implement Moore’s Law to include all aspects of heterogeneous systems and develop architectures, methodologies, designs, components, materials and manufacturable integration schemes that will shrink system footprint and improve power and performance.
Is Moore’s Law dead or not? It depends on your perspective. Last week at ECTC 2016, Rozalia Beica, Dow Electronic Materials, gathered a prestigious group of senior executives from the world’s leading microelectronics research institutes to discuss Life after Moore’s Law. Panelists included Marie-Noelle Semeria, CEA-Leti; Dim Lee Kwong, IME; Luc van den hove, imec; CP Wong, NCAP; and Subu Iyer, UCLA CHIPS. Each discussed the strategy they will pursue to continue innovations for next-generation computing technologies, with or without Moore’s Law.
UCLA’s Subramaniam Iyer believes the industry needs to rethink its future direction.
“We are at a crossroads. Current chip design is nearing its capacity. The time, expense, and effort needed to make major inroads have grown exponentially. We need a transformational shift in how our systems are designed and put together. Moore’s law is no longer about scaling a chip, but about scaling the system.” ~ Excerpt from the letter to attendees of the CHIPS kick-off meeting at UCLA. This is the mission of the new Center for Heterogeneous Integration and Performance Scaling (CHIPS) that was launched with a kick-off meeting at UCLA on November 2, 2015.